1. Field of the Invention
The present invention relates, in general, to input/output (I/O) circuitry for integrated circuits and, more particularly, to an I/O circuit for asynchronous edge detection that can be implemented using logic synthesis tools.
2. Relevant Background
Modern integrated circuits (ICs) are developed using synthesis flow based design techniques to reduce the design time and increased reliability of the designed products. Synthesis based techniques use synthesis tools that allow a designer to describe a circuit in a high level language (e.g., hardware description language or HDL). The synthesis tool is a complex set of computer programs that compile the HDL description into circuit schematics, programming instructions for programmable logic devices (e.g., field programmable gate arrays) or mask layouts for implementation in a semiconductor device. Synthesis tools allow a circuit to be simulated, emulated, and debugged before committing significant resources to reducing the circuit to hardware.
One limitation of synthesis-based techniques is that they are limited to synchronous design elements and do not allow for unclocked or unlatched feedback loops. The hardware description language requires or imposes timing constraints on each device. This prohibits the use of simple combinational logic feedback latches (e.g., SR latches, D latches, and the like) to handle asynchronous signals. However, interface circuits that serve to couple signals from one integrated circuit to another require a means for detecting and responding to asynchronous signals.
In the past, when multiple circuits were used in a system on a single circuit board or on a single chip, a common clock line synchronized the multiple integrated circuits. The common clock allowed synchronous action and synchronous communication between all the integrated circuits on a circuit board. However, modern integrated circuits are designed modularly and may use circuits that run on varying clock speeds in the same system or even on a single IC chip.
For example, a microprocessor having a first clock speed and a digital signal processing unit having a second clock speed may be integrated on a single IC. In portable equipment and energy saving "green" systems it is desirable to temporarily reduce clock speed of some of the circuits to save power. During this powered down state the IC should desirably capture inputs from other circuits so that it can power up and respond to those inputs. Hence, modern integrated circuits require communication between multiple devices each of which may be running at different and variable clock speeds.
One solution to this problem is to incorporated edge triggered latches in the design. The edge-triggered latch can capture and hold an input signal even while the circuit is powered down because it does not need a clock signal to latch the incoming data. However, as set out above, edge triggered latches are incompatible with synthesis-based designed techniques. In contrast to the rapid, automated design available with synthesis tools, edge triggered latches must be manually placed into a design from existing circuit libraries. Moreover, edge triggered latches require several transistors that increase size and cost of the integrated circuit.
Another solution that does not use edge triggered latches is to force the asynchronous request signal from one integrated circuit to extend one or more clock cycles in duration. The extended clock cycle ensures that the pulse will be detected by the receiving integrated circuit. This solution burdens the transmitting integrated circuit since it must be aware of the receiving circuit's clock frequency. This is often not practical when integrated circuits are allowed to vary the clock frequency to conserve power. Also, forcing the transmitting device to hold its signal for a number of clock cycles unnecessarily slows the transmitting device's performance and may commit latches and I/O circuitry within the transmitting device so that they are unavailable for other functions.
What is needed is a circuit that can be implemented using synthesis-based design techniques and mimics an edge triggered latch to receive asynchronous signals from neighboring integrated circuits without requiring extended clock cycles or edge triggered latches.